The dimensions of semiconductor field effect transistors (FETs) have been steadily shrinking over the last thirty 30 years or so, as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate.
For a given device length, the amount of current drive for an FET is defined by the device width (w). Current drive scales proportionally to device width, with wider devices carrying more current than narrower devices. Different parts of integrated circuits (ICs) require the FETs to drive different amounts of current, i.e., with different device widths, which is particularly easy to accommodate in planar FET devices by merely changing the device gate width (via lithography).
With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional geometries that will facilitate continued device performance improvements. One such class of devices is a FinFET.
A FinFET is a double gate FET in which the device channel is within a semiconducting “Fin” having a width w and height h, where typically w<h. The gate dielectric and gate are positioned around the Fin such that charge flows down the channel on the two sides of the Fin and optionally along the top surface.
FinFET devices typically include a fully depleted body in the Fin that provides several advantages over a conventional FET. These advantages include, for example, nearly ideal turn off in the sub-threshold regime, giving lower off-currents and/or allowing lower threshold voltages, no loss to drain currents from body effects, no ‘floating’ body effects (often associated with some silicon-on-insulator (SOI) FETs), higher current density, lower voltage operation, and reduced short channel degradation of threshold voltage and off current. Furthermore, FinFETs are more easily scaled to smaller physical dimensions and lower operating voltages than conventional FETs and SOI FETs.
Definition of both the semiconducting Fins and the source/drain regions by a single mask has been extremely difficult in the prior art due to rounding of the corners where the Fins join the wide source/drain areas. As a result, there is neither room for alignment of the gate to the active semiconducting material, nor room for extension implants into the sidewalls of the Fins.
A mask to separately pattern source and drain regions of silicon to link the Fins provides a solution for the rounding problem, but adds an extra overlay for added mask to the Fins, leaving little room for extension implants between the source and drain linking regions and the gate electrode, unless the registration of the various masks is nearly perfect.
In view of the above, there is a need for providing a method that can define both the Fins and the source/drain regions by a single mask that avoids the rounding problem mentioned above as well as the need for using additional overlays.
SUMMARY OF THE INVENTION
The present invention provides a method that overcomes the above mentioned problems using simple rectangular shapes to define the Fins which avoid rounding and yet joins the Fins by a deposition of a selective silicon-containing material post gate etch. More specifically, the present invention provides a method of forming a semiconductor structure including a plurality of FinFET devices in which crossing masks are employed in providing linear patterns to define relatively thin Fins along with a chemical oxide removal (COR) process. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material.
In general terms, the present invention provides a method that includes the steps of:
providing a structure including a plurality of patterned material stacks comprising a nitride layer on top of an oxide hardmask on a surface of semiconductor substrate and a plurality of patterned photomasks which cross over said plurality of patterned material stacks;
performing a chemical oxide removal step that laterally etches at least exposes sidewalls of said oxide hardmask of each material stack not protected by one of said patterned photomasks;
removing the plurality of patterned photomasks to expose patterned material stacks including a laterally etched oxide hardmask beneath said nitride layer;
performing an anisotropic etching process selective to the laterally etched oxide hardmask to remove said nitride layer and at least an upper portion of any semiconducting material of said semiconductor substrate not protected by said laterally etched oxide hardmask to form Fins; and
forming a plurality of gate regions that cross over said Fins.
Optionally, the laterally etched oxide hardmask is removed by exposing upper portions of the semiconducting material of the semiconductor substrate previously protected by said laterally etched oxide hardmask, wherein portions of said exposed upper portions of the semiconducting material of the semiconductor substrate previously protected by said laterally etched oxide hardmask define the Fins.
Each of the Fins produced by the inventive method are then merged by forming a Si-containing material between each of the Fins. The Si-containing material prevents rounding of corners of each Fin with their corresponding source/drain region. The source/drain regions are located within wider end portions of each Fin that where previously protected by said plurality of patterned masks that cross over said plurality of patterned stacks. The wider end portions of each Fin are substantially square; i.e., little or no rounding of the corners of the wider end portions occurs in the present invention.
The present invention also relates to the semiconductor structure that is fabricated using the above processing steps. In general terms, the semiconductor structure of the present invention comprises:
a plurality of FinFET devices located on a surface of a semiconductor substrate, each of said FinFET devices including an elevated semiconducting layer that has wider end portions relative to its middle portion, a gate region that crosses said middle portion, and source/drain regions within said wider end portions; and
a Si-containing material located between said elevated semiconducting layer that joins each elevated semiconducting layer.